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아래와 같이 콜로퀴움을 개최하오니 많이 참석해 주시기 바랍니다. 4시부터 2층 라운지세미나실에 다과를 준비하오니 많은 참석 부탁드립니다 아 래 1. 제 목: Downscaling of self-aligned, all-printed polymer thin-film transistors 2. 연 사: 노 용 영 박사 ( ETRI ) 3. 일 시: 2008년 9월 19일(금) 오후4:30 4. 장 소: 물리학과세미나실(31355호실) 5. 초 록: Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it suffers from poor resolution, large overlap capacitances, and film thickness limitations resulting in slow circuit speed and high operating voltages. In the presentation, I will talk about how we can achieve perfect downscaling polymer transistors with sub-micrometer channel length. A self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 – 400 nm. The use of a cross-linkable polymer gate dielectric with 30-50 nm thickness ensures that basic scaling requirements are fulfilled and operating voltages are below 5 V. The device architecture minimizes contact resistance effects enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes the parasitic overlap capacitance to low values of down to 0.2-0.6 pF/mm and provides a significant improvement of transistor switching speed over 1.5 MHz. Our self-aligned process provides a path for improving the performance of printed organic transistor circuits by downscaling while remaining compatible with the requirements of large-area, flexible electronics manufacturing. 다운을 받으시려면 아래의 링크를 클릭해주세요. http://physics.skku.ac.kr/ppt/0919.pdf
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